1. Field of the Invention
This disclosure relates to vector processing, and more particularly to enhanced predicate registers.
2. Description of the Related Art
Vector processors have traditionally been utilized to exploit data-level parallelism (DLP) in software programs. The architecturally fixed-width element width of conventional vectors can present challenges in exploiting the potential parallelism available with data elements that are smaller than the element width. For example, if a processor supports concurrent operations on vectors of 32-bit elements, but a particular vector has elements that are only 8 or 16 bits wide, then processing resources that are fully utilized when operating on vectors of 32-bit elements may be underutilized when operating on the smaller-element vectors.